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74VCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
January 1998 Revised February 2002
74VCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16240 contains sixteen inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The 74VCX16240 is designed for low voltage (1.4V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74VCX16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.4V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD 2.5 ns max for 3.0V to 3.6V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL)
24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74VCX16240MTD Package Number MTD48 Package Descriptions 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OEn I0-I15 O0-O15 Description Output Enable Input (Active LOW) Inputs Outputs
(c) 2002 Fairchild Semiconductor Corporation
DS500099
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74VCX16240
Connection Diagram
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H Inputs OE3 L L H Inputs OE4 L L H I12-I15 L H X I8-I11 L H X I4-I7 L H X I0-I3 L H X Outputs O0-O3 H L Z Outputs O4-O7 H L Z Outputs O8-O11 H L Z Outputs O12-O15 H L Z
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance
Functional Description
The 74VCX16240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs.
Logic Diagram
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74VCX16240
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATED Outputs Active (Note 3) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to VCC +0.5V -50 mA -50 mA +50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 4)
Power Supply Operating Input Voltage Output Voltage (VO) Output in Active States Output in 3-State Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V VCC = 1.4V to 1.6V Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused inputs must be held HIGH or LOW.
1.4V to 3.6V
-0.3V to +3.6V
0V to VCC 0.0V to 3.6V
24 mA 18 mA 6 mA 2 mA -40C to +85C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 VIL LOW Level Input Voltage 2.7-3.6 2.3-2.7 1.65-2.3 1.4 - 1.6 VOH HIGH Level Output Voltage IOH = -100 A IOH = -12 mA IOH = -18 mA IOH = -24 mA IOH = -100 A IOH = -6 mA IOH = -12 mA IOH = -18 mA IOH = -100 A IOH = -6 mA IOH = -100 A IOH = -2 mA 2.7-3.6 2.7 3.0 3.0 2.3-2.7 2.3 2.3 2.3 1.65-2.3 1.65 1.4 - 1.6 1.4 VCC - 0.2 2.2 2.4 2.2 VCC - 0.2 2.0 1.8 1.7 VCC - 0.2 1.25 VCC - 0.2 1.05 V Min 2.0 1.6 0.65 x VCC 0.65 x VCC 0.8 0.7 0.35 x V CC 0.35 x V CC V V Max Units
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74VCX16240
DC Electrical Characteristics
Symbol VOL Parameter LOW Level Output Voltage
(Continued)
VCC (V) 2.7-3.6 2.7 3.0 3.0 2.3-2.7 2.3 2.3 1.65-2.3 1.65 1.4 - 1.6 1.4 1.4-3.6 1.4-3.6 0 1.4-3.6 1.4-3.6 2.7-3.6
Conditions IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 24 mA IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 100 A IOL = 6 mA IOL = 100 A IOL = 2 mA
Min
Max 0.2 0.4 0.4 0.55 0.2 0.4 0.6 0.2 0.3 0.2 0.35 5.0 10 10 20 20 750
Units
V
II IOZ IOFF ICC ICC
Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Increase in ICC per Input
0 VI 3.6V 0 VO 3.6V VI = VIH or VIL 0 (VI, VO) 3.6V VI = VCC or GND VCC (VI, VO) 3.6V (Note ) VIH = VCC -0.6V
A A A A A
Note 5: Outputs disabled or 3-STATE only.
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74VCX16240
AC Electrical Characteristics
Symbol tPHL tPLH Parameter Propagation Delay
(Note 6)
Conditions VCC (V) 3.3 0.3 2.5 0.2 1.8 0.15 TA = -40C to +85C Min 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 Max 2.5 3.0 6.0 12.0 3.5 4.1 8.2 16.4 3.5 3.8 6.8 13.6 0.5 0.5 0.75 1.5 ns ns Figures 1, 3, 4 Figures 5, 7, 8 ns Figures 1, 3, 4 Figures 5, 7, 8 ns Figures 1, 2 Figures 5, 6 Units Figure Number
CL = 30 pF, RL = 500
CL = 15 pF, RL = 2k tPZL tPZH CL = 15 pF, RL = 2k tPLZ tPHZ CL = 15 pF, RL = 2k tOSHL tOSLH Output to Output Skew (Note 7) CL = 15 pF, RL = 2k
Note 6: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1
Output Enable Time
CL = 30 pF, RL = 500
Output Disable Time
CL = 30 pF, RL = 500
CL = 30 pF, RL = 500
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP Parameter Quiet Output Dynamic Peak VOL Conditions CL = 30 pF, VIH = VCC, VIL = 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 TA = +25C Typical 0.25 0.6 0.8 -0.25 -0.6 -0.8 1.5 1.9 2.2 V V V Units
Capacitance
Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Conditions VCC = 1.8, 2.5V or 3.3V, VI = 0V or VCC VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V TA = +25C Typical 6 7 20 pF pF pF Units
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74VCX16240
AC Loading and Waveforms (VCC 3.3V 0.3V to 1.8V 0.15V)
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open 6V at VCC = 3.3 0.3V; VCC x 2 at VCC = 2.5 0.2V; 1.8V 0.15V GND FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V 1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
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74VCX16240
AC Loading and Waveforms (VCC 1.5V 0.1V)
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open VCC x 2 at VCC = 1.5 0.1V GND FIGURE 5. AC Test Circuit
FIGURE 6. Waveform for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 1.5V 0.1V VCC/2 VCC/2 VOL + 0.1V VOH - 0.1V
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74VCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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